National Semiconductor
DS92LV1021 and DS92LV1210
10-bit Bus LVDS Serializer / Deserializer pair
This LVDS serializer/deserialzer pair can provide a 40MByte/sec serial
copper link of up to 10 meters length. It is intended that the user handle
all functions such as framing and encoding in external logic. The pair
provides only the serialization and deserialization functions.
MANUFACTURER'S DEVICE DESCRIPTION
The DS92LV1021 serializer transforms a 10-bit wide parallel CMOS/TTL
data bus, at up to 40MHz, into a single high speed Bus LVDS serial data
stream with embedded clock. The DS92LV1210 deserializer receives the Bus
LVDS serial data stream and transforms it back into a 10-bit wide parallel
data bus and separate clock. The DS92LV1021 may transmit data over heavily
loaded backplanes or 10 meters of cable. The reduced cable, PCB trace count
and connector size saves cost and makes PCB design layout easier.
Clock-to-data and data-to-data skew are eliminated since one output will
transmit both clock and all data bits serially. A power-down pin is used
to save power, by reducing supply current when either device is not in
use. The Serializer has a synchronization mode that should be activated
upon power-up of the device. The Deserializer will establish lock to this
signal within 1024 cycles, and will flag Lock status. The embedded clock
guarantees a transition on the bus every 12-bit cycle; eliminating transmission
errors due to charged cable conditions. The DS92LV1021 output pins may
be TRI-STATE to achieve a high impedance state. The PLL can lock
to frequencies between 16 MHz and 40 MHz.
FEATURES
|
Parallel |
Serial |
| Throughput |
160-400 Mbps (10-bit mode) |
480 MBaud |
| # bits |
10 |
1 LVDS diff. pair |
| Frequency |
16-40 MHz |
|
| Signal levels |
LVTTL (3.3V) |
Bus LVDS |
| Synchronous/sync with idles/asynchronous |
Synchronous |
| Input data needs coding |
no |
| Error detection |
no |
| Power consumption, serializer/transmitter |
32mA typical, 55mA max at 40MHz |
| Power consumption, deserializer/receiver |
44mA typical, 75mA max at 40MHz |
| Power supply voltage |
+3.3 V |
| Package size |
28-pin SSOP |
| Technology |
unknown |
| Radiation hardness |
unknown |
| Price |
~$10. for serializer, ~$10. for deserializer |
COMMENTS
This serializer/deserializer pair is part of National's line of Bus
LVDS components. They can be used point-to-point, multi-drop, or to
build a "bus". The DS92LV1021/1210 pair is very simple and assumes that
the user provides the intelligence for coding/decoding, framing and control
by means of an ASIC or FPGA. This gives considerable flexibility in its
use.
-
The chipset has three active states of operation: initialization, data
transfer, and resynchronization, and two passive states: power down and
tri-state.
-
The serializer requires a setup time of 1ns but a hold time of up to 6.5ns
(typical 4.5ns).
-
Either the rising or falling edge of the clock can be chosen to clock the
data.
-
Each 10-bit transfer is framed by a start bit (high) and a stop bit (low).
-
See comments on Sync and Lock below.
RADIATION HARDNESS
All CMOS design, but no radiation hardness data on the chip is available
from National.
ISSUES FOR LHC APPLICATIONS
-
synchronisation on start-up and, possibly, during running
-
receiver signals 'Lock' back to the transmitter via a separate line to
the 'Sync' input. It may be possible to tie the Sync input to active.
-
not known yet under what conditions resync actually occurs during running
-
maximum 10 meters at 40MHz
-
radiation hardness unknown
-
BusLVDS allows a maximum common mode 1 Volt offset between transmitter
and receiver
DOCUMENTATION
National Semiconductor's
DS92LV1021/1210 "Product folder"
DS92LV1021/1210
Data Sheet (358KB pdf)
LVDS Signal Quality:
Cable Drive Measurements using Eye Patterns Test Report #3 (130KB pdf)
National Semiconductor
LVDS Home Page (lots of links)
BLVDS White
Paper (PDF Format) Signal integrity and validation of Bus LVDS (BLVDS)
technology in heavily loaded backplanes.
RELATED COMPONENTS
National Semiconductor
LVDS 28-bit and 21-bit Channel Link 0.840 to 1.8Gbit/sec
USERS
Reliability being tested at the Weizmann Institute - Lorne
Levinson
CONTACT
ATLAS: Lorne Levinson
- Weizmann Institute of Science
National Semiconductor
CERN - High
Speed Interconnect
Lorne Levinson -
9 April 1999 - Disclaimer